1. Technical Field
The present invention relates generally to integrated circuit (IC) design, and more particularly, to a method, system and program product for detecting and preventing design rule errors due to overlapping shapes.
2. Related Art
Integrated circuits are commonly designed on computerized design systems that allow for layout and design rule spacing evaluation. Design rule spacing constraints are implemented to prevent IC parts from being too close together such that, for example, shorts may result. Accordingly, design rule constraints are often based on metal width. Design shapes are generally represented in computerized design systems as shapes or collections of shapes. When two or more metal shapes of an IC design overlap, the resulting metal shape has the potential to require a larger space than the individual shapes due to its increased width. Conventional gridded detail routers, such as IBM Signal Router, do not consider overlapping shapes and may route wires such that spacing constraints are violated by the overlapping shapes. Similarly, conventional power routers have the same problem. Heretofore, these design rule errors were only detected by design rule checking (DRC) late in the design cycle. As a result, routing steps and DRC is often repeated numerous times before an IC design is design rule compliant.
In view of the foregoing, there is a need in the art for a solution that addresses the problems of the related art.